1. Field of the Invention
The present invention relates generally to a method of forming a semiconductor device, and more particularly, to a method for pulling down a fin structure after an inner spacer is formed, and an outer spacer is then formed, so as to protect the fin structure and the gate structure.
2. Description of the Prior Art
In order to increase the carrier mobility of semiconductor structure, applying tensile stress or compressive stress to a gate channel has been widely practiced. For instance, if a compressive stress were to be applied, it has been common in the conventional art to use the selective epitaxial growth (SEG) technique to form an epitaxial structure such as a silicon germanium (SiGe) epitaxial layer in a silicon substrate. As the lattice constant of the SiGe epitaxial layer is greater than the lattice constant of the silicon substrate, thereby producing stress to the channel region of PMOS transistor, the carrier mobility is increased in the channel region and speed of MOS transistor is improved accordingly. Conversely, a silicon carbide (SiC) epitaxial layer could be formed in the silicon substrate to produce tensile stress for the gate channel of an NMOS transistor.
Despite the aforementioned approach improving the carrier mobility in the channel region, the complexity of the overall process also increases accordingly. For instance, the conventional approach typically forms a recess in the silicon substrate, deposits a buffer layer in the recess and then forms an epitaxial layer thereafter. Nevertheless, the buffer layer formed by this approach typically has uneven thickness, such that in most cases the bottom portion of the buffer layer is approximately three to five times thicker than the sidewall portion of the buffer layer. This causes negative impacts such as short channel effect or drain induced barrier lowering (DIBL) and degrades the quality and performance of the device.